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Features
* * * * * * * * * * * * * * * *
First-in First-out Dual Port Memory 16384 bits x 9 Organization Fast Flag and Access Times: 15, 30 ns Wide Temperature Range: -55C to +125C Programmable Half Full Flag Fully Expandable by Word Width or Depth Asynchronous Read/Write Operations Empty, Full and Half Flags in Single Device Mode Retransmit Capability Bi-directional Applications Battery Back-up Operation: 2V Data Retention TTL Compatible Single 5V + 10% Power Supply No Single Event Latch Up Below an LET threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 30 Krads (according to MIL-STD-883 TM1019) Quality grades: QML Q and V with SMD 5962-93177 and ESSC with Specification 9301/48
Description
The M672061H implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information are required for the Atmel FIFOs. Address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. The Retransmit pin resets the Read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system. Using an array of eight transistors (8T) memory cell, the M672061H combines an extremely low standby supply current (typ = 0.1 A) with a fast access time at 15 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 2 W. For military/space applications that demand superior levels of performance and reliability the M672061H is processed according to the methods of the latest revision of the MIL PRF 38535 (Q and V) or ESCC 9000.
Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag
M672061H
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Block Diagram
Pin Configuration
DIL ceramic 28-pin 300 mils FP 28-pin 400 mils
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Pin Description
Pin Name I0 - 8 Q0 - 8 W R RS EF FF XO/HF XI FL/RT VCC GND Description Inputs Outputs Write Enable Read Enable Reset Empty Flag Full Flag Expansion Out/Half-Full Flag Expansion IN First Load/Retransmit Power Supply Ground
Data In (I0 - I8) Reset (RS)
Data inputs for 9-bit data Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both internal read and write pointers to the first location. A reset is required after power-up before a write operation can be enabled. Both the Read Enable (R) and Write Enable (W) inputs must be in the high state during the period shown in Figure 2 (i.e. tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Otherwise, pulse write (or read) low during the reset operation loads the Programmable Half Full Flag register from the data Inputs I0 - I8 (or data outputs Q0 - Q8) (shown in figure 2). In these two cases the Full Flag and the Programmable Half Full Flag are reseted to high and the Empty Flag to low.
Figure 1. Reset (no write to Programmable Half Full Flag register)
Notes:
1. EF, FF and HF may change status during reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS.
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Figure 2. Reset (write (read) to Programmable Half Full Flag register)
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be maintained in the rise time of the leading edge of the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any current read operation. Once half the memory is filled, and during the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and remain in this state until the difference between the write and read pointers is less than or equal to half of the total available memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF, allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 - Q8) will return to a high impedance state until the next Read operation. When all the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the "final" read cycle, but inhibiting further read operations while the data outputs remain in a high impedance state. Once a valid write operation has been completed, the Empty Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO stack is empty, the internal read pointer is blocked from R, so that external changes to R will have no effect on the empty FIFO stack. This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to ground to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by connecting the Expansion In (XI) to ground. The M672061H can be set to retransmit data when the Retransmit Enable Control (RT) input is pulsed low. A retransmit operation will set the internal read point to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. The retransmit feature is intended for use when a number of writes are equal to or less than the depth of the FIFO has occured since the last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), in accordance with the relative locations of the read and write pointers.
First Load/Retransmit (FL/RT)
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Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain modes. The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes. The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer is equal to the write pointer, indicating that the device is empty. This is a dual-purpose output. In the single device mode, when Expansion In (XI) is connected to ground, this output acts as an indication of a half-full memory. The M672061H offers a variable offset for the Half Full condition. The offset is loaded into a register during a reset cycle. When RS is low, the Programmable Half Full Flag (PHF) can be loaded from the DATA inputs I0 - I8 by pulsing W low or from the DATA outputs Q0 - Q8 by pulsing R low. The offset options are listed in table 1. If PHF is not loaded during the reset cycle, the default offset will be the half of the total memory of the device. The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to the Programmable offset (if the Half Full Flag register has been loaded during the reset cycle) or the half of the total memory (if the Half Full register has not been loaded during the reset cycle). After half the memory is filled and on the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last memory location.
Full Flag (FF)
Empty Flag (EF) Expansion Out/Half-full Flag (XO/HF)
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state.
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Functional Description
Single Device Mode
A single M672061H may be used when the application requirements are for 16384 words or less. The M672061H is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 3). In this mode the Half-Full Flag (HF), which is an active low output, is shared with Expansion Out (XO). Figure 3. Block Diagram of Single 16384 x 9
HF (HALF-FULL FLAG) WRITE (W) HF 9 DATAIN (I) (Q) (EF) (RT) 9 DATAOUT (R) READ
FULL FLAG (FF) RESET (RS)
EMPTY FLAG RETRANSMIT
EXPANSION IN (XI)
M672061H
Width Expansion Mode
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any device. Figure 4 demonstrates an 18-bit word width by using two M672061H. Any word width can be attained by adding additional M672061H.
Figure 4. Block Diagram of 16384 bits x 18 FIFO Memory Used in Width Expansion Mode
Note:
Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width expansion configuration. Do not connect any output control signals together.
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Table 1. Programmable Half Full Flag Offset
I8 0 0 0 ... 1 ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 16384-64 16384-32 0 0 0 0 0 0 0 0 8192 (Half Full) Default Offset I7 0 0 0 I6 0 0 0 I5 0 0 0 I4 0 0 0 I3 0 0 0 I2 0 0 0 I1 0 0 1 I0 0 1 0 Offset 0 32 64
Table 2. Reset and Retransmit Single Device Configuration/Width Expansion Mode
Inputs Mode Reset Retransmit Read/Write Note: RS 0 1 1 RT X 0 1 XI 0 0 0 Read Pointer Location Zero Location Zero Increment(1) Internal Status Write Pointer Location Zero Unchanged Increment(1) EF 0 X X Outputs FF 1 X X HF 1 X X
1. Pointer will increment if flag is high.
Table 3. Reset and First Load Truth Table Depth Expansion/Compound Expansion Mode
Inputs Mode Reset First Device Reset All Other Devices Read/Write Note: RS 0 0 1 FL 0 1 X XI
(1) (1) (1)
Internal Status Read Pointer Location Zero Location Zero X Write Pointer Location Zero Location Zero X EF 0 0 X
Outputs FF 1 1 X
1. XI is connected to XO of previous device. See Figure 5.
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Depth Expansion (Daisy Chain) Mode
The M672061H can be easily adapted for applications which require more than 16384 words. Figure 5 demonstrates Depth Expansion using three M672061H. Any depth can be achieved by adding additional 672061H. The M672061H operates in the Depth Expansion configuration if the following conditions are met: 1. The first device must be designated by connecting the First Load (FL) control input to ground. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be connected to the Expansion In (XI) pin of the next device. See Figure 5. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires that all EF's and all FFs be ORed (i.e. all must be set to generate the correct composite FF or EF). See Figure 5. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode.
Compound Expansion Module Bidirectional Mode
It is quite simple to apply the two expansion techniques described above together to create large FIFO arrays (see Figure 6). Applications which require data buffering between two systems (each system being capable of Read and Write operations) can be created by coupling M672061H as shown in Figure 7 Care must be taken to ensure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode. Two types of flow-through modes are permitted: a read flow-through and a write flowthrough mode. In the read flow-through mode (Figure 18) the FIFO stack allows a single word to be read after one word has been written to an empty FIFO stack. The data is enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the first write edge and remains on the bus until the R line is raised from low to high, after which the bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating temporary reset and then will be set. In the interval in which R is low, more words may be written to the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; however, the same word (written on the first write edge) presented to the output bus as the read pointer will not be incremented if R is low. On toggling R, the remaining words written to the FIFO will appear on the output bus in accordance with the read cycle timings. In the write flow-through mode (Figure 19), the FIFO stack allows a single word of data to be written immediately after a single word of data has been read from a full FIFO stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading edge of W. The W line must be toggled when FF is not set in order to write new data into the FIFO stack and to increment the write pointer.
Data Flow - Through Modes
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Figure 5. Block Diagram of 49152 x 9 FIFO Memory (Depth Expansion)
M672061H
M672061H
M672061H
Figure 6. Compound FIFO Expansion
Notes:
1. For depth expansion block see section on Depth Expansion and Figure 4. 2. For Flag detection see section on Width Expansion and Figure 3
Figure 7. Bidirectional FIFO Mode
H
H
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Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC - GND): ............................. -0.5V to 7.0V Input or Output voltage applied: ... (GND -0.3V) to (Vcc +0.3V) Storage temperature:.................................... -65 C to +150C
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Parameters
Table 4. DC Test Conditions TA = -55C to +125C; Vss = 0V; Vcc = 4.5V to 5.5V
Parameter ICCOP (1) ICCSB(2) ICCPD(3) Notes: Description Operating supply current Standby supply current Power down current M672061H-30 110 5 400 M672061H-15 120 5 400 Unit mA mA A Value Max Max Max
1. Icc measurements are made with outputs open. 2. R = W = RS = FL/RT = VIH. 3. All input = Vcc Parameter ILI(1) ILO(2) VIL(3) VIH(3) VOL(4) VOH(4) C IN
(5)
Description Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage Output high voltage Input capacitance Output capacitance
M672061H 1 1 0.8 2.2 0.4 2.4 8 8
Unit A A V V V V pF pF
Value Max Max Max Min Max Min Max Max
C OUT(5) Notes: 1. 2. 3. 4. 5.
0.4 Vin Vcc. R = VIH, 0.4 VOUT VCC. VIH max = Vcc + 0.3V. VIL min = -0.3V or -1V pulse width 50 ns. For XI input, VIH= 2.8V Vcc min, IOL = 8 mA, IOH = -2 mA Guaranteed but not tested.
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AC Parameters
AC Test Conditions
Input pulse levels: Gnd to 3.0V Input rise/Fall times: 5 ns Input timing reference levels: 1.5V Output reference levels: 1.5V Output load: See Figure 8 Figure 8. Output Load
(1)
Note:
1. Includes jig and scope capacitance. M672061H- 30 Min Max M672061H- 15 Min Max
Table 5. AC Test Conditions
Symbol (1) Symbol (2) Parameter (3) (4) Unit
Read Cycle TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ Write Cycle TWLWL TWLWH TWHWL TDVWH TWHDX Reset Cycle TRSLWL TRSLRSH TWHRSH tRSC tRS tRSS Reset cycle time Reset pulse width (5) Reset set-up time 40 30 30 25 15 20 ns ns ns tWC tWPW tWR tDS tDH Write cycle time Write pulse width(5) Write recovery time Data set-up time Data hold time 40 30 10 18 0 25 15 10 9 0 ns ns ns ns ns tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ Read cycle time Access time Read recovery time Read pulse width (5) Read low to data low Z (6) Write low to data low Z (6) (7) Data valid from read high Read high to data high Z (6) 40 10 30 0 5 5 30 20 25 10 15 0 3 5 15 15 ns ns ns ns ns ns ns ns
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Table 5. AC Test Conditions (Continued)
Symbol (1) Symbol (2) Parameter (3) (4) M672061H- 30 Min TRSHWL Retransmit Cycle TRTLWL TRTLRTH TWHRTH TRTHWL Flags TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH Expansion TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL tXOL tXOH tXI tXIR tXIS Read/Write to XO low Read/Write to XO high XI pulse width XI recovery time XI set-up time - - 30 10 10 30 30 - - - - - 15 10 10 15 15 - - - ns ns ns ns ns tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset to EF low Reset to HF/FF high Read low to EF low Read high to FF high Read width after EF high Write high to EF high Write low to FF low Write low to HF low Read high to HF high Write width after FF high - - - - 30 - - - - 30 30 30 30 30 - 30 30 30 30 - - - - - 15 - - - - 15 25 25 25 25 - 15 20 30 30 - ns ns ns ns ns ns ns ns ns ns tRTC tRT tRTS tRTR Retransmit cycle time Retransmit pulse width(5) Retransmit set-up time(6) Retransmit recovery time 40 30 30 10 - - - - 25 15 15 10 - - - - ns ns ns ns tRSR Reset recovery time 10 Max - M672061H- 15 Min 10 Max - ns Unit
1. 2. 3. 4. 5. 6. 7.
STD symbol. ALT symbol. Timings referenced as in ac test conditions. All parameters tested only. Pulse widths less than minimum value are not allowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode.
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Figure 9. Asynchronous Write and Read Operation
Figure 10. Full Flag from Last Write to First Read
Figure 11. Empty Flag from Last Read to First Write
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Figure 12. Retransmit
Note:
1. EF, FF and PHF may change status during Retransmit, but flags will be valid at tRTC
Figure 13. Empty Flag Timing W
t
WEF
EF
t
RPE
R
Figure 14. Full Flag Timing
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Figure 15. Programmable Half-Full Flag Timing
Figure 16. Expansion Out
Figure 17. Expansion In
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Figure 18. Read Data Flow - Through Mode
Figure 19. Write Data Flow - Through Mode
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Ordering Information
Reference Number MMCP-672061HV-15-E(1) SMCP-672061HV-15SCC SMCP-672061HV-30SCC 5962-9317710QTC 5962-9317709QTC 5962-9317710VTC 5962-9317709VTC 5962D9317710VTC 5962D9317709VTC MMDP-672061HV-15-E SMDP-672061HV-15SCC SMDP-672061HV-30SCC 5962-9317710QNC 5962-9317709QNC 5962-9317710VNC 5962-9317709VNC 5962D9317710VNC 5962D9317709VNC MM0 -672061HV-15-E(1) MM0 -672061HV-15SV Note:
(1)
Temperature Range 25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C
Speed 15 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 15 ns
Package SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 Die Die
Quality Flow Engineering Samples ESCC ESCC QML Q QML Q QML V QML V QML V RHA QML V RHA Engineering Samples ESCC ESCC QML Q QML Q QML V QML V QML V RHA QML V RHA Engineering Samples QML V
1. Contact Atmel for availability.
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Package Drawings
28-lead Side Braze (300 mils)
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28-lead Flat Pack (400 mils)
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Atmel Corporation
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